1. Field of the Invention
This invention relates to structures which improve the high frequency performance of bipolar discrete or integrated transistors.
It may easily be demonstrated that in some bipolar amplifier configurations, such as the class A tuned output common-emitter (CE) stage, maximization of the maximum oscillation frequency (f.sub.max) yields optimal high frequency performance. The major components of f.sub.max are the base resistance and the collector base junction capacitance (C.sub.jc). These device parameters need to be minimized in order to maximize f.sub.max.
The collector base capacitance is a function of epitaxial layer doping and of device area. The base resistance is a function of the emitter aspect ratio (width to length or B/L ratio) which somewhat defines the overall transistor size.
Minimum base resistance is commonly achieved by using at least two base contacts. Also, the emitter length (where "length" is the dimension of the emitter in the direction of base current flow, i.e. perpendicular to the base contacts) should be minimized and will be defined by the design rules selected.
The base area is defined by:
(1) the emitter surface area; PA1 (2) the base contact surface area; PA1 (3) the spacing between the base contacts and emitter window; and PA1 (4) a peripheral component which includes the sidewalls and the plane area from the junction edge and the base contacts.
It is clear that special technologies such as oxide isolation and polysilicon base contacts may reduce the r.sub.bb C.sub.jc figure of merit, where r.sub.bb is the base resistance and C.sub.jc is the collector base depletion layer capacitance. However, the present invention relates primarily to the layout aspects of the transistor.
2. Description of the Prior Art
Various layout techniques have been developed over the years for bipolar transistors. Most tend to maximize the emitter periphery to area ratio in order to optimize high frequency and high power operation.
The best-known layouts used in the prior art to attempt to achieve the above goals are: (1) the overlay transistor (see J. Andeweg and T. H. J. van den Hurk, "A discussion of the design and properties of a high-power transistor for single sideband applications", IEEE Trans. Electron Devices, vol. ED-17, September 1970, pp. 717-724; H. F. Cooke, "Microwave transistors: theory and design", Proc. IEEE, vol. 59, August 1971, pp. 1163-1181; D. R. Carley, P. L. McGeough and J. F. O'Brien, "The overlay transistor", Electronics, Aug. 23, 1965, pp. 71-77); (2) interdigitated structure (see Andeweg and van den Hurk, supra, and H. F. Cooke, supra); and (3) "mesh" emitter transistors also known as the emitter grid or matrix (see M. Fukuta, H. Kisaki and S. Maekawa, "Mesh emitter transistor", Proc. IEEE (Lett.), vol. 56, April 1968, pp. 742-743; Andeweg and van den Hurk, supra; and H. F. Cooke, supra).
These geometries are compared in the literature (see Fukata et al, supra, and Andeweg and van den Hurk, supra), but generally f.sub.max is not considered (i.e. r.sub.bb or C.sub.jc are not evaluated) and the emitter areas are not compared. These geometries are therefore qualitatively discussed below in order to better compare them.
The most common layout technique used today, shown in FIG. 1, consists of an emitter 1 with parallel base contacts 2, one on each side of the emitter stripe. The design rules of Table 1 below are assumed:
TABLE 1 ______________________________________ Assumed Design Rules ______________________________________ Minimum contact 2a .times. 2a Metal width 4a Metal to metal 4a Metal to contact edge 2a Contact to diffusion 2a where a is one unit length. ______________________________________ (Washed emitter process is assumed, but it is clear that the above applie to any other fabrication process (standard, polysilicon emitter, etc.))?
Most of the area of the base contacts 2 and the peripheral component 3 of the device shown in FIG. 1 may be considered wasted area, and this area increases as the emitter width B is increased.
One alternative to reduce the wasted area is to use an interdigitated layout which basically shares a central base contact between two adjacent emitter stripes. Interdigitated structures yield a small area saving for wide emitter layouts (B/L of 18 or more for the above design rules). A slight reduction in collector-base area comes from the fact that the central base contact is shared by two adjacent emitters, permitting the elimination of a small area which would otherwise be duplicated. One advantage of the interdigitated structure is a reduction in emitter series resistance due to metallization.
In the case of an overlay structure, the overall base diffusion area is relatively large for a given emitter area, due to the extra spacing between each emitter island. The base resistance, although reduced due to an increase in emitter periphery, is not minimized due to the presence of the now large extrinsic component. The f.sub.max frequency is not much improved when compared to the interdigitated structure, at relatively low current levels.
A mesh structure is such that an improved f.sub.max is expected when compared to an overlay structure. This comes about due to a reduction in base diffusion area for a given emitter area, due to a minimization of the base contact area. The base resistance is reduced when compared to the interdigitated or overlay transistors, since the emitter surrounds the minimum dimension contacts. The problem associated with the mesh layout technique is that the current distribution in the emitter diffusion will be mostly limited to the centre section, where the metal is located. This current distribution will not minimize the base resistance since the effective emitter width is less than the perimeter of the emitter diffusion. Also, emitter area is increased, which will reduce the transition frequency, f.sub.t of the transistor.